1. Field of the Invention
The present invention relates to a test circuit of a semiconductor memory and, particularly, to a semiconductor memory test circuit for aging memory cells of a dynamic RAM (DRAM).
2. Description of the Prior Art
In order to increase the integration density of semiconductor integrated circuit, the miniaturization of semiconductor integrated circuit has been enhanced year by year and this tendency is remarkable in semiconductor memories. Since, when the miniaturization of semiconductor memory is enhanced, the sizes of gates and contacts of transistors thereof are reduced and mutual distance between transistors is also reduced, the breakdown of insulating film due to voltage stress becomes a problem. In order to prevent such problem from occurring on a user side, the aging for preliminarily actualizing potential defects has been performed on a manufacturer side.
In the aging of semiconductor memory, BT (Bias.cndot.Temperature) test is usually used to effectively age a capacitive oxide film and an insulating film under high voltage and high temperature condition.
FIG. 11 is a circuit diagram of a conventional semiconductor memory test circuit, in which a voltage application to memory cells is improved. The semiconductor memory test circuit is constructed with a HVC (Half-Vcc) circuit 11 for applying a voltage, which is a half of a power source voltage Vcc, to electrodes of paired memory cells and a control circuit 12 for controlling an output signal First Polysilicon at Half-Vcc (HVC1P) of the HVC circuit 11 to the electrodes of the paired memory cells and an output signal Digital Balance Potential at Half-Vcc (HVCD) thereof to a sense amplifier.
The semiconductor memory test circuit receives control signals including an input signal HVC-Stop for stopping the operation of the HVC circuit, an aging input signal AGING for performing an aging operation, an analysis input signal ANA for analyzing operation and a power source input signal Power-on-Trigger for switching the power source.
The output signal HVC1P is supplied to the electrodes of paired memory cells of the DRAM memory. The potential of the output signal HVC1P is kept at Vcc/2 in a usual operation, Vcc in the aging operation and ground level (GND) during a failure analysis operation. FIG. 12 is a timing chart showing the potential levels of the output signals HVC1P and HVCD of the semiconductor memory test circuit shown in FIG. 11 at a time when the power source is turned ON. An upper portion of FIG. 12 shows these output signals when the result of test is normal and a lower portion thereof shows the output signals when the result of test is failure. In FIG. 12, when the power source is turned on at a time instance t=0, the potential of the output signal HVC1P is changed from the ground level to Vcc/2 during a period as short as several milliseconds. This potential must be higher than the potential of the output signal HVCD. In the normal operation, the potential of the output signal HVC1P is always kept at higher than that of the output signal HVCD and, in the failure operation, the potential of the output signal HVCD becomes higher than that of the output signal HVC1P.
The output signal HVCD is supplied to a balance potential input of the sense amplifier. The potential of the output signal HVCD is in Vcc/2 level during the normal operation, the aging operation and the failure analysis operation. At a time when the power source is turned on, the potential of the output signal HVCD starts to rise from the ground level at a time instance delayed from the turning on of the power source to Vcc/2 level within a time period of several milliseconds. Practically, some offset (several mV) may be added to the output signal HVC1P and/or the output signal HVCD. In this description, however, it is assumed that there is no such offset added.
In order to control the power supply to the HVC circuit, the input signal HVC-Stop controls the state of the node D whether the potential of the latter is made in Vcc/2 level or an impedance thereof is made high.
When the aging operation input or the analysis operation input to be described is made H level, the input signal HVC-Stop is made H level to perform the aging operation or the failure analysis operation. Although it is possible to measure small leak currents of the HVC1P output and the HVCD output by making the input signal AGING or the input signal ANA in H level, it is impossible to make both the input signal AGING and ANA in H level simultaneously.
The input signal AGING switches the output signal HVC1P between Vcc and Vcc/2. In the aging operation, the output signal HVC1P becomes Vcc level by making the input signal AGING in H level. In the normal operation, the output signal HVClP becomes Vcc/2 by making the input signal AGING in L level. The voltage stress of the capacitor becomes effective by this aging operation.
The input signal ANA switches the level of the output signal HVClP between the ground level and Vcc/2 level. In the failure analysis, the output signal HVClP becomes ground level bymaking the input signal ANA in H level and, in the normal operation, the output signal HVC1P becomes Vcc/2 by making the input signal ANA in L level. By this failure analysis, the insulation breakdown of the capacitor can be detected.
The input signal Power-on-Trigger switches the output signal HVCD between the same level as that of the output signal HVC1P and high impedance. When the input signal Power-on-Trigger is made in H level, the transistor Qn7 is turned ON, so that the output signal HVCD becomes in the same level as that of the output signal HVC1P. When the input signal Power-on-Trigger is made in L level, the transistor Qn7 is turned OFF, so that the output signal HVCD becomes high impedance. The output signal HVC1P must rise at higher rate than that of the output signal HVCD reliably at the time tO at which the power source is turned ON. Since signals, which rise from L level to H level in the time period of several milliseconds from t0 to t1, are supplied from other circuits, the input signal Power-on-Trigger is provided (FIG. 12) Japanese Patent Application Laid-open No. H4-146588 discloses a technique for switching a voltage level of the output signal HVC1P between the normal operation and the aging operation. FIG. 13 is a circuit diagram of a semiconductor memory test circuit disclosed in the above Japanese Patent Application Laid-open No. H4-146588. The disclosed semiconductor memory test circuit includes an input terminal 50 for applying a control voltage when a test is performed and an output terminal connected to electrodes of paired memory cells. The input terminal 50 is connected to a node NA through a 6-stage diode circuit 51 for detecting an applied potential and to a node NB through a 3-stage diode circuit 52 for detecting an applied potential. The node NA is connected to a ground through a 4-stage node pull-down transistor circuit 53 and to an input of an inverter 55. The node NB is connected to the ground through a 4-stage node pull-down transistor circuit 54 and to an input of an inverter 57. An output of the inverter 55 is connected through an inverter 56 to a first input of a 2-input EXOR gate 58 and a gate of an N channel type MOS transistor 62 connected between a node NC connected to the electrodes of the paired memory cells and the ground. An output of the inverter 57 is connected to a second input of the 2-input EXOR gate 58 and a gate of an N channel MOS transistor 60 connected between the node NC and a 1/2 Vcc generator circuit 59. An output of the 2-input EXOR gate 58 is connected to a gate of a P channel MOS transistor 61 connected between the node NC and the power source Vcc.
Upon a voltage VIN applied to the input terminal 50, the diode circuits 51 and 52 become conductive with voltages proportional to the numbers of the N channel MOS transistors constituting the diode circuits, respectively. In this case, the value of the input voltage VIN, with which the diode circuits 51 and 52 are turned ON, are VA and VB (VA&gt;VB). Since the N channel MOS transistors constituting the node pull-down stages 53 and 54 are in ON state, the nodes NA and NB are kept in L level.
In a case where VB&gt;VIN, the MOS transistors 61 and 62 are turned OFF and the MOS transistor 60 is turned ON. Therefore, the output to the electrode of the paired memory cells becomes Vcc/2 level.
In a case where VA&gt;VIN&gt;VB, the MOS transistors 60 and 62 are turned OFF and the MOS transistor 61 is turned ON. Therefore, the output to the electrode of the paired memory cells becomes Vcc level.
In a case where VIN&gt;VA, the MOS transistors 60 and 61 are turned OFF and the MOS transistor 62 is turned ON. Therefore, the output to the electrode of the paired memory cells becomes ground level.
As above mentioned, it is possible to switch the output signal level between Vcc/2, Vcc and ground level by the value of the input voltage VIN applied to the input terminal 50.
In the Japanese Patent Application Laid-open No. H4-146588, the voltage level Vcc/2 is produced by the control transistor 60 connected between the node NC and the 1/2 Vcc generator circuit 59. Therefore, the boot phenomenon to be described later may occur. Further, since the transistors 61 and 62 connected between the power source Vcc and the ground are controlled through a logic circuit, there may be a case where both the transistors 61 and 62 are turned ON in an unstable state when the power source is turned ON causing a through-current to flow. Incidentally, there is no description in the Japanese Patent Application Laid-open No. H4-146588 of a control of an output to a sense amplifier for providing an effective voltage stress between a first contact and a gate.
The reason for that the control transistor connected between the circuit for supplying the voltage in 1/2 Vcc level causes the boot phenomenon to occur will be described with reference to FIG. 11. The operation speed of the transistor Qn5 for controlling the output signal to the electrode of paired memory cells is delayed when the power source is turned ON, for two reasons. One of the reasons is an increase of the threshold voltage. That is, the voltage between a source and drain of the transistor Qn5 is in Vcc/2 level and a potential difference between the source and a substrate thereof is large compared with that of a transistor having a source at ground potential. With such large potential difference between the source and the substrate, the threshold voltage of the transistor becomes high. The other reason is a delay in operation of the NOR1 gate which drives the gate of the transistor Qn5. That is, the NOR circuit performs the power supply and signal transmission through a wiring having arbitrary length. Therefore, if the length of the wiring is large, the drive of the transistor Qn5 is delayed. In such case, there is a possibility that the rising rates of the output voltage to of the electrodes of paired memory cells and the output voltage to the sense amplifier become close.